Integrated circuit devices are widely used in consumer and commercial applications. As integrated circuit devices become more highly integrated, the reliability of insulation between conductive line interconnections may impact the reliability of the devices. An example of a conductive line is a bit line in an integrated circuit memory device.
FIG. 1 is a plan view of an integrated circuit memory device with a bit line in a conventional capacitor over bit line (COB) structure. FIGS. 2A to 2E are cross-sectional views of the device for illustrating a method for manufacturing the device shown in FIG. 1, wherein the cross-sectional views are taken along a line II—II in FIG. 1. FIGS. 3A to 3E are cross-sectional views of the device for illustrating the method for manufacturing the device shown in FIG. 1, wherein the cross-sectional views are taken along a line III—III in FIG. 1. FIG. 4 is a cross-sectional view of the device, taken along a line IV—IV in FIG. 1.
Referring to FIG. 2A and FIG. 3A, there is provided an integrated circuit substrate such as a semiconductor substrate 100 having an active region 101 and a field region. A shallow trench isolation (STI) film 105 is formed in the field region of the substrate 100 by a known STI method.
A gate 110, a first interlayer insulation layer 120 and a contact pad 130 are formed on the substrate 100. The contact pads 130 are connected to impurity regions (not shown) of a predetermined conductivity type formed in the active regions 101 through contacts 125, respectively. As shown in FIG. 4, the gate 110 comprises a gate oxide layer 111, a gate electrode material layer 113, a gate capping layer 115 stacked in order, and a sidewall spacer 117.
A second interlayer insulation layer 140 is formed on the first interlayer insulation layer 120 and then etched to form a contact hole 145 exposing corresponding ones of contact pads 130 which are to be connected to a conductive line such as a bit line in the following process.
A barrier metal layer 151 and a metal layer 155 for a bit line contact pad are sequentially formed on the substrate 100 including the bit line contact hole 145 and then etched using a chemical mechanical polishing (CMP) process to form a bit line contact pad 150 comprised of the barrier metal layer 151 and the metal layer 155 in the bit line contact hole 145.
Referring to FIG. 2B and FIG. 3B, a barrier metal layer 161, a conductive material layer 163 for a bit line and a bit line capping layer 165 are formed on the second interlayer insulation layer 140 and then patterned to form a bit line 160. The bit line 160 includes the barrier metal layer 161, the conductive material layer 163 and the bit line capping layer 165 and is connected to the bit line contact pad 150 through the bit line contact hole 145.
Referring to FIG. 2C and FIG. 3C, an insulation layer such as a nitride layer is formed on the bit line 160 and the second interlayer insulation layer 140, and etched back to form a bit line spacer 170. In more detail, the capping layer 165 is formed on the upper layer of the bit line 160 and the bit line spacer 170 is formed at a sidewall of the bit line 160. Accordingly, the bit line 160 is surrounded by the insulation material on its upper surface and sidewalls to provide isolation.
Referring to FIG. 2D and FIG. 3D, a third interlayer insulation layer 180 is formed on the second interlayer insulation layer 140 and the bit line 160. Then the second and third interlayer insulation layers 140 and 180 are etched to form a storage node contact hole 185 exposing corresponding one of contact pads 130 which is to be connected to a storage node of a capacitor in the following process.
Referring to FIG. 2E and FIG. 3E, a polysilicon layer is formed on the third interlayer insulation layer 180 to be filled with the storage node contact hole 185, and then etched using a known CMP process for a node separation to form a storage node contact pad 190. The storage node contact pad 190 is connected to the exposed one of the contact pads 130 via the storage node contact hole 185. Next, a capacitor (not shown) is formed to connect to the storage node 190 by a conventional capacitor formation process, thereby fabricating the device.
As described above, the bit line is insulated from the storage node contact pad by forming the bit line spacer on the sidewall thereof. However, the width of the bit line spacer may become narrower as the devices become more highly integrated. Accordingly, it may be difficult to provide electrical insulation reliability between the bit line and the adjacent storage node contact pad.
Furthermore, it may be desired to reduce contact resistance of the storage node contact pad in order to provide high performance devices. To decrease the contact resistance, the contact area of the storage node contact pad may be enlarged. However, if the contact area is increased, the insulation reliability may be lowered. Accordingly, it may be difficult to decrease the contact resistance of the storage node contact pad without deteriorating the insulation reliability.